1. Filed of the Invention
The present invention relates to a memory array, particularly to a method for operating a low-cost EEPROM (Electrically Erasable Programmable Read Only Memory) array.
2. Description of the Related Art
The CMOS (Complementary Metal Oxide Semiconductor) technology has been a normal process for fabricating ASIC (Application Specific Integrated Circuit). Flash memories and EEPROM (Electrically Erasable Programmable Memory) have been widely used in electronic products because their data will not volatilize but can be erased and programmed electrically.
Non-volatile memories are programmable, storing charges to vary gate voltages of transistors, or not storing charges to preserve the original gate voltages of transistors. In erasing a non-volatile memory, the charges stored in the non-volatile memory are eliminated to resume the initial state of the memory. Refer to FIG. 1 and FIG. 2 respectively schematically showing a circuit and a circuitry layout of a conventional non-volatile memory. As shown in FIG. 1 and FIG. 2, a non-volatile memory comprises a plurality of memory cells. Each memory includes a transistor 10 and a capacitor structure 12. Two bit lines are arranged between two neighboring one-bit memory cells. Thus, the area efficiency is reduced. Refer to FIG. 3 schematically showing a sectional view of a memory cell. As shown in FIG. 3, the capacitor structure 10 is disposed on one side of the transistor 10. Such a structure would occupies larger area and further reduce the area efficiency.
In order to overcome the abovementioned problems of the conventional technology, the Inventors develop a small-area EEPROM array and propose a method for operating the same in a low-current and low-voltage environment to massively program the memory cells of the same simultaneously.